As circuit density has increased, increasing production yield has become more difficult in the manufacture of integrated circuit memory devices. There are basically two techniques to improve the production yield of the memory devices. The first technique is to enhance the quality of the manufacturing process so as to reduce the occurrence of defective memory cells. The second technique is to modify the construction of a memory cell array, such that a portion of the memory cell array is set aside as a redundant memory section. The redundant memory cells are accessed whenever it is determined that an incoming address corresponds to a defective portion of the memory cell array. On-chip logic circuitry employed to store defective memory addresses includes multiple fuse groups wherein individual fuses are either opened or closed to represent a logic state. The memory devices can also be designed with a number of different operation modes. One method to select an operation modes is to use fuses (i.e., option fuses). The fuses employed in the redundancy and mode option are normally either filament type, or a laser-blown type fuses. Such fuses are made of polysilicon or molybdenum silicide and are formed on a field oxide layer at the level of a wiring layer.
Referring to FIGS. 1 through 3, a conventional arrangement of fuses of a semiconductor memory device is shown. A plurality of fuses 10a-10d are formed spaced apart an equal distance from each other, and a fuse window 20 is provided over the construction in order to define an opening region 11 (or 11') of FIGS. 2 and 3. Metal lines M are arranged for peripheral circuit areas adjacent to the fuse region. The fuse window restricts the formation of other circuit components and permits a laser beam to be introduced there into through insulation layer 14 (of FIGS. 2 and 3) so as to blow out the fuses. After the fuses are formed, oxide and nitride insulation layers 14, 16 are deposited on the resulting structure. And a region of insulation layer 16 and a portion of insulation layer 14 are removed to a predetermined thickness, thereby forming an opening therein. Successful fuse cutting by a laser beam in a subsequent process step depends on the accuracy of such a process. As shown in FIG. 2, however, edge portions 11a and 11b of opening region 11 are not sharp. Because of this, fuses 10a through 10d are not positioned identically with respect to the surface of the insulation layer 14. In this example, the distance between the surface of the insulation layer 14 and fuses 10b and 10c is shorter than the distance between the surface of the insulation layer 14 and fuses 10a and 10d, due to the existence of the thick inner edge portions 11a and 11b. As a result, the fuses near the inner edge portions 11a and 11b are difficult to be blown out even by an accurately aimed laser beam.
Widening an opening region can be one way to overcome such a problem. But it is not an ultimate solution because widening also increases a layout area. Also, in order to enhance the compensation rate for hard defects in a chip, it is desirable to include a greater redundancy capability by minimizing the width of each fuse region, thus allowing more fuses in a given redundancy area. Since the fuse size is fixed, elongation of the opening undesirably increases the layout size.